PIC18F1230T-I/ML【PDF 306/318 页】IC PIC MCU FLASH 2KX16 28QFN

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Sheet目录3871

302页 303页 304页 305页 [306页]307页 308页 309页 310页

PIC18F1230/1330

DS39758D-page 88

2009 Microchip Technology Inc.

TABLE 10-1:

PORTA I/O SUMMARY

Pin

Function

TRIS

Setting

I/O

Type

Description

RA0/AN0/INT0/

KBI0/CMP0

RA0

DIG

LATA<0> data output; not affected by analog input.

TTL

PORTA<0> data input; disabled when analog input enabled.

AN0

ANA

Analog input 0.

INT0

External interrupt 0.

KBI0

TTL

Interrupt-on-change pin.

CMP0

ANA

Comparator 0 input.

RA1/AN1/INT1/

KBI1

RA1

DIG

LATA<1> data output; not affected by analog input.

TTL

PORTA<1> data input; disabled when analog input enabled.

AN1

ANA

Analog input 1.

INT1

External interrupt 1.

KBI1

TTL

Interrupt-on-change pin.

RA2/TX/CK

RA2

DIG

LATA<2> data output; not affected by analog input. Disabled when

CVREF output enabled.

TTL

PORTA<2> data input. Disabled when analog functions enabled;

disabled when CVREF output enabled.

DIG

EUSART asynchronous transmit.

DIG

EUSART synchronous clock.

IST

RA3/RX/DT

RA3

DIG

LATA<3> data output; not affected by analog input.

TTL

PORTA<3> data input; disabled when analog input enabled.

ANA

EUSART asynchronous receive.

DIG

EUSART synchronous data.

ITTL

RA4/T0CKI/AN2/

VREF+

RA4

DIG

LATA<4> data output.

PORTA<4> data input; default configuration on POR.

T0CKI

Timer0 external clock input.

AN2

ANA

Analog input 2.

VREF+

ANA

A/D reference voltage (high) input.

MCLR/VPP/RA5/

FLTA

MCLR

Master Clear (Reset) input. This pin is an active-low Reset to the device.

VPP

ANA

Programming voltage input.

RA5

Digital input.

FLTA(1)

Fault detect input for PWM.

RA6/OSC2/CLKO/

T1OSO/T1CKI/AN3

RA6

DIG

LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.

PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.

OSC2

ANA

Oscillator crystal output or external clock source output.

CLKO

ANA

Oscillator crystal output.

T1OSO(2)

ANA

Timer1 oscillator output.

T1CKI(2)

Timer1 clock input.

AN3

ANA

Analog input 3.

RA7/OSC1/CLKI/

T1OSI/FLTA

RA7

DIG

LATA<7> data output. Disabled in external oscillator modes.

TTL

PORTA<7> data input. Disabled in external oscillator modes.

OSC1

ANA

Oscillator crystal input or external clock source input.

CLKI

ANA

External clock source input.

T1OSI(2)

ANA

Timer1 oscillator input.

FLTA(1)

Fault detect input for PWM.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note

Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H.

Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.

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